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A 2.5-V sigma-delta modulator for broadband communications applications

机译:适用于宽带通信应用的 2.5V Σ-Δ 调制器

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Oversampled sigma-delta (ΣΔ) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-μm double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply.
机译:过采样Σ-Δ (ΣΔ) 调制器为实现高分辨率模数 (A/D) 转换器提供了许多优势。本文探讨了在过采样率受到技术限制的情况下,如何在高分辨率ΣΔ调制器中采用过采样和反馈,将信号带宽扩展到几兆赫兹的范围内。本文介绍了一种适合采用 2.5V 电源供电的 2-2-1 级联多位架构,并引入了一种称为分区数据加权平均的线性化技术来抑制带内数模转换器 (DAC) 误差。基于所提出的拓扑结构的实验原型已集成在0.5 μm双多晶三金属CMOS技术中。全差分双采样开关电容积分器使调制器能够在 4Msample/s 奈奎斯特转换速率下实现 95dB 动态范围,过采样比为 16。实验调制器采用 2.5V 电源时功耗为 150mW。

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