...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Journal of Solid-State Circuits >Low-power synchronous-to-asynchronous-to-synchronous interlocked pipelined CMOS circuits operating at 3.3-1.5 GHz
【24h】

Low-power synchronous-to-asynchronous-to-synchronous interlocked pipelined CMOS circuits operating at 3.3-1.5 GHz

机译：低功耗同步至异步至同步互锁流水线CMOS电路，工作频率为3.3-1.5 GHz

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Interlocked pipelined CMOS (IPCMOS), a new asynchronous set of clock circuits suitable for high-frequency and low-power operation, is described. In IPCMOS, the reduced power results from enabling the local clocks only when there is an operation to perform and from a simple single-stage latch. The single-stage latch can be used because the locally generated clocks driving adjacent stages are not enabled simultaneously. The combination of enabling the clocks only when there is an operation to perform and the simple latch can lower power by a factor of five to ten times in many applications. In IPCMOS, the staggered local clocks also result in a significant reduction of dynamic L di/dt noise. In addition to the locally generated interlocked clocks and the single-stage latch, unique circuits that combine the function of a static NOR and an input switch are key to achieving high performance and minimizing the overhead in the interlocking. In a 0.18-μm bulk CMOS technology, these circuits drive a path through a typical 64-b multiplier stage at 3.3-4.5 GHz on an experimental chip. IPCMOS also provides a way to implement the interface between asynchronous and synchronous portions of a design, thereby giving the approach a great deal of flexibility by making it possible to drop IPCMOS into portions of an existing synchronous design.
机译：本文介绍了联锁流水线CMOS（IPCMOS），这是一组适用于高频和低功耗操作的新型异步时钟电路。在IPCMOS中，功耗降低是由于仅在有操作要执行时才启用本地时钟和简单的单级锁存器。之所以可以使用单级锁存器，是因为驱动相邻级的本地生成时钟不会同时启用。在许多应用中，仅在需要执行操作时启用时钟和简单的锁存器相结合，可以将功耗降低 5 到 10 倍。在IPCMOS中，交错的本地时钟也显著降低了动态L di/dt噪声。除了本地生成的联锁时钟和单级锁存器外，结合静态 NOR 和输入开关功能的独特电路是实现高性能和最大限度地减少联锁开销的关键。在 0.18μm 块状 CMOS 技术中，这些电路在实验芯片上以 3.3-4.5GHz 的频率驱动一条路径，通过典型的 64b 乘法器级。IPCMOS还提供了一种在设计的异步和同步部分之间实现接口的方法，从而通过将IPCMOS放入现有同步设计的某些部分，为该方法提供了极大的灵活性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号