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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs
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A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

机译：一种使用静态锁存器和双极性电压可编程反熔丝电路的封装后位修复方案，用于高密度DRAM

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摘要

A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of V{sub}(CC) and - V{sub}(CC), alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4 for 0.16-μm triple-well 256-M SDRAM.
机译：新提出了一种双极性电压可编程反熔丝电路方案和位修复方案，用于封装后修复。对于故障位修复，所提方案中的反熔断器通过V{sub}（CC）和-V{sub}（CC）的双极性电压进行编程，缓解了器件永久击穿等高压问题，实现了比原方案更小的反熔断器电路布局面积。此外，使用高效的位修复方案代替传统的线路修复方案，从而减少了冗余位的布局面积。此外，冗余位使用静态锁存器代替动态存储单元，消除了冗余区域中可能存在的缺陷，使这种位修复方案更加稳健，并避免了老化应力问题。通过制造商用 DRAM 产品，对于 0.16μm 三孔 256-M SDRAM，通过 1 位封装后修复实现高达 2.4% 的良率提高。

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