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机译:用于运动估计的完整流水线并行 CORDIC 架构
机译:Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
机译:Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC
机译:261 MHz Parallel Tree Architecture for Full Search Variable Block Size Motion Estimation in H.264/AVC
机译:Parallel pipelined histogram architecture via C-slow retiming
机译:VLsI implementation of discrete cosine transform using a new asynchronous pipelined architecture.