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首页> 外文期刊>journal of low power electronics and applications >Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

机译：SAFEPOWER架构在安全、高能效混合临界系统中的实验评估

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With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
机译：随着工业界对更大、更快、更高效系统的需求不断增长，越来越多的内核被集成在单个芯片上。此外，通过同时执行尽可能多的流程，它们的性能进一步最大化。即使在铁路和航空电子等安全关键领域，也引入了多核处理器，但受到严格的认证规定。随着内核数量的不断扩大，成本效益的重要性也越来越大。提高这种片上系统 （SoC） 成本效益的一种方法是增强 SoC 处理其功耗的方式。通过提高电源效率，由于电池寿命延长，SoC的可靠性得到提高。其次，通过减少能源消耗，SoC 中排放的热量减少，从而减少冷却设备。尽管能源效率已经得到深入研究，但这些节能方法尚未在安全关键领域得到应用。欧盟项目SAFEPOWER（具有低功率要求的安全可靠的混合临界系统）针对这一研究空白，旨在引入可认证的方法来提高混合临界系统的电源效率。本文概述了用于低功耗混合临界系统的SAFEPOWER参考架构，这是该项目最重要的成果。此外，还演示了该参考架构在新型铁路联锁和飞控航空电子系统中的应用，展示了实现高达 37% 的节能能力，同时仍能保证时间触发的任务执行和基于时间触发的 NoC 通信。

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