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The impact of induced gate noise when simultaneously power and conjugate noise-matching MOS transistors

机译:同时为噪声匹配的MOS晶体管供电和共轭噪声时感应栅极噪声的影响

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摘要

A method for simultaneously power matching and conjugate noise matching a MOS transistor for radio frequency applications is presented in this paper. Experimental results from a 0.6μm nMOS transistor show that the magnitude of input reactanceequals the optimum noise reactance (i.e., X{sub}in = X{sub}out). Using this result, we provide a method that can be used to match the optimum noise resistance to the source resistance. The described method uses the number of gate fingers as a parameter to conjugately match for noise.
机译:该文提出了一种在射频应用中同时对MOS晶体管进行功率匹配和共轭噪声匹配的方法。0.6μm nMOS晶体管的实验结果表明,输入电抗的大小等于最佳噪声电抗(即X{sub}in = X{sub}out)。利用这一结果,我们提供了一种方法,可用于将最佳噪声电阻与源电阻相匹配。所描述的方法使用栅极指的数量作为参数来共轭匹配噪声。

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