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A low-power array multiplier using separated multiplication technique

机译:一种采用分离乘法技术的低功耗阵列乘法器

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This brief proposes a separated multiplication technique that can be used in digital image signal processing such as finite impulse response (FIR) filters to reduce the power dissipation. Since the 2-D image data have high spatial redundancy, such that the higher bits of input pixels are hardly changed, the redundant multiplication of higher bits is avoided by separating multiplication into higher and lower parts. The calculated values of the higher bits are stored in memory cells, caches, such that they can be reused when a cache hit occurs. Therefore, the dynamic power is reduced by about 14 in multipliers by using the proposed separated multiplication technique (SMT) and in a 1-D 4-tap FIR filter by about 10.
机译:本简报提出了一种分离乘法技术,可用于数字图像信号处理,例如有限脉冲响应 (FIR) 滤波器,以降低功耗。由于二维图像数据具有较高的空间冗余性,因此输入像素的较高位几乎不会改变,因此通过将乘法分成较高和较低的部分,可以避免较高位的冗余乘法。较高位的计算值存储在存储单元、缓存中,以便在发生缓存命中时可以重复使用它们。因此,使用所提出的分离乘法技术(SMT)将乘法器的动态功率降低约14%,而在一维4抽头FIR滤波器中,动态功率降低约10%。

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