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首页> 外文期刊>IEEE Transactions on Automatic Control >A limit cycle suppressing arithmetic format for digital filters
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A limit cycle suppressing arithmetic format for digital filters

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摘要

In this paper it will be shown that any digital filter with a stable transfer function can be implementedfree of limit cycles, if block floating point arithmetic is used in conjunction with the so-calledexponent saturation and flush-to-zero option. A certain system dependent minimum block mantissalength is required. Limit cycle suppression is achievable regardless of the structure and thequantization format. This format is simple to implement even on fixed point processors and offershigh dynamic range.

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