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Novel topologies for time-interleaved delta-sigma modulators

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摘要

An elegant way to decrease the operation speed or equivalently to increase the conversion bandwidth of △∑ modulators is via exploitation the time-interleaving approach. Recently, we have proposed a novel method to obtain efficient architectures for time-interleaved △∑ modulators. In this paper, we extend this method to a sub-class of modulators containing cascaded integrators with weighted feedforward summation and cascaded integrators with distributed feedback as well as feedforward branch topologies. A new time-interleaving concept based on zero-insertion interpolation is also proposed, which eliminates the high-sampling-rate multiplexer at the input stage, resulting in a further significant simplification in hardware complexity. In this approach, the input signal is sampled at the operation frequency of the channels and applied only to the first channel, whereas all other channels are fed with zeros all the time. The low-pass filter at the output of the modulator serves two purposes: 1) it rejects the spectral replicas of the input signal and 2) it attenuates the out-of-band quantization noise.

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