In the context of the Virtual Socket Interface system on a chip interface for embedded blocks, a behavioral model of a digital-to-analog converter is presented. A generic model, which is used for high-level design exploration, as well as anextracted model after synthesis, are presented. Both static (integral nonlinearity, differential nonlinearity) and dynamic behavior (glitch behavior, settling time) are modeled accurately. Power and area estimators are derived as well. The model resultsin efficient system simulations.
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