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Estimation of propagation delay considering short-circuit current for static CMOS gates

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摘要

We present a formula of propagation delay for static CMOS logic gates considering short-circuitcurrent and current flowing through gate capacitance and using the ,th power law MOSFET modelwhich considers velocity saturation effects. The short circuit current is represented by a piecewise-linear function, which enables detailed analysis of the transient behavior of a CMOS inverter. Wefound that the error of our formulas for a CMOS inverter is less than 8 from circuit simulation inmost cases of our experiments. We also applied these formulas to logic gates made up of series-parallel connected MOSFET's by replacing the series-connected MOSFET's with an equivalentMOSFET. The influence of short-circuit power on delay, which is explicitly modeled in our formula,is numerically demonstrated such that the influence becomes large with slow input transition andsmall output load capacitance.

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