Pass transistor logic (PTL) has advantages over standard CMOS designs in terms of layout density,circuit delay, and power consumption and is well suited for pipelined circuits. In this paper wedevelop a decision-diagram-based model, the 123-decision diagram, which can be used to efficientlysynthesize PTL circuits, and we investigate multilevel logic synthesis techniques for complex,pipelined PTL networks using this model. Experiments on a large number of benchmark circuitsshow that PTL networks synthesized using our techniques are significantly more economic in termsof silicon area compared to those using existing techniques.
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