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首页> 外文期刊>IEEE sensors journal >A Power Efficient Image Sensor Readout With On-Chip delta-Interpolation Using Reconfigurable ADC
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A Power Efficient Image Sensor Readout With On-Chip delta-Interpolation Using Reconfigurable ADC

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摘要

In this paper, a low-power readout using reconfigurable cyclic ADC for CMOS image sensors is proposed. It reduces the total number of pixels to be read by taking advantage of pixel correlation. The required number of ADC operations is reduced, resulting in power saving. In contrast to the existing pixel correlation-based approaches, which focus only on the intensity differences, in the proposed method, the polarity of the differences is also taken into account. It helps in preserving fine edges representing features such as texture. The discarded or unread pixels are interpolated on-chip while reconfiguring the ADC input range according to the interpolation step size. Furthermore, this reduces the number of ADC conversion cycles by 25 to 50 for interpolation steps of 16 LSB and 64 LSBs, respectively. The ADC is designed and fabricated in UMC 180-nm CMOS technology, and the proposed method is verified for standard test images. The reconstructed images incorporating ADC non-linearities result in average Pratt's FoM values of 0.88, 0.86, and 0.81 for 60, 70, and 74 compression, respectively. The corresponding best values achieved by the existing approaches are 0.86, 0.80, and 0.77, respectively. The improvement in FoM is observed due to the consideration of polarity information. The proposed technique results from 33 to 50 power saving for 80 compression in 512 x 512 image, using reconfigurable ADC. Therefore, it is suitable for a power efficient CMOS sensor design.

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