A sub-60-μA multimodal analog front-end and ultralow energy biosensing CMOS SoC is presented. A 35-μA photoplethysmography (PPG) signal chain that consumes five times lower power than state of the art has been demonstrated. An SNR of 80 dBFS was achieved using circuit and system techniques that enable sub-1 analog duty cycling. Input signal-aware, on-the-fly, real-time data path adaptation algorithms implemented on an external microcontroller and synchronized by an ultralow power on-chip FSM along with a 1.3-μW, 14-b, 1-kSPS SAR ADC further lower system energy. A programmable, asynchronous reset capacitive amplifier (PARCA) with noise efficiency factor (NEF) of 4.8 and dx/dt analog feature extractor demonstrates energy efficient electrocardiogram (ECG) capture. A wearable platform using this SoC that simultaneously captures ECG plus PPG and wirelessly transmits the heart rate using Bluetooth low energy every 2 s to a smartphone lasts for greater than five days from a 250-mAhr battery.
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