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外文期刊>IEEE Journal of Solid-State Circuits
>Universal-V{sub}(dd) 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
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Universal-V{sub}(dd) 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
A universal-V{sub}(dd) 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-μm enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V. Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V. The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation.
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