A multigigabit DRAM technology was developed that features a low-noise 6F{sup}2 open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-Flash fuse. This technology, which can be used to fabricate a 0.13-μm 180μmm{sup}2 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm{sup}2, 200-MHz array-cycle, 256-Mb test chip with 0.109-μm{sup}2 cells.
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