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首页> 美国政府科技报告 >Switch-Level Timing Simulation of MOS VLSI (Metal-Oxide-Semiconductor Very Large-Scale Integrated) Circuits.
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Switch-Level Timing Simulation of MOS VLSI (Metal-Oxide-Semiconductor Very Large-Scale Integrated) Circuits.

机译：mOs VLsI（金属氧化物半导体超大规模集成电路）的开关级时序仿真。

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This report deals with the development of a fast and accurate simulation tool for very-large-scale integrated (VLSI) circuits consisting of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented in this thesis can handle only n-channel MOS(NMOS) circuits, but are easily extendible to handle complementary MOS(CMOS) circuits as well. The algorithms presented in this report have been implemented in a computer program called MOSTIM. In all the circuits simulated thus far, MOSTIM provides timing information with an accuracy of within 10% of that provided by SPICE2, at approximately two orders of magnitude faster in simulation speed. (Author)

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