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Electrostatic Discharge (ESD) Simulator Experiment (Testing of Some Switches/Relays for Application to an ESD Simulation Circuit)

机译：静电放电（EsD）模拟器实验（用于EsD仿真电路的某些开关/继电器的测试）

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Over the past few years, many models have been proposed in an attempt to accurately simulate the human electrostatic discharge using lumped passive networks. The complexity of these models range from a simple R-C network to networks incorporating inductance and multiple discharge effects. It has been generally accepted to simulate the human touch by a bounceless switch that will provide a consistently reproducible output waveform for device ESD sensitivity testing. This paper presents the results of an investigation/testing conducted to evaluate different types of relays/switches used as the switching mechanism for an ESD simulator test set-up. The network used is the simplest, human body model consisting of a single 100 pF capacitor discharging via a single 1.5 Kohm resistor.

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作者
Vrachnas, S. A.;
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年度 1983
页码 p.1-30
总页数 30
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
Simulators; Electric discharges; Electrical networks; Electric relays; Electric switches; Electrical resistance; Humans; Inductance; Setting(Adjusting); Human body; Passive systems; Capacitance; Simulation; Test methods; Reproducibility; Resistors; Networks; Waveforms;

机译：模拟器;放电;电气网络;电气继电器;电气开关;电阻;人体;电感;设置（调整）;人体;无源系统;电容;模拟;测试方法;再现性;电阻器;网络;波形;

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专利

1. ESD-level circuit simulation impact of interconnect RC-delay on HBM and CDM behavior (Reprinted from Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 2000) [J] . Mergens MPJ., Wilkening W., Kiesewetter G., Journal of Electrostatics . 2002,第1期

机译：ESD电路仿真对互连RC延迟对HBM和CDM行为的影响（转载自《电气过应力/静电放电研讨会论文集》，2000年）
2. Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits [J] . Pengyu Lai, Xianrui Li, Hui Wang, IEICE Electronics Express . 2019,第18期

机译：轨道基静电放电（ESD）保护电路寄生双极晶体管的研究
3. Electrostatic Discharge Protection for RF Integrated Circuits: New ESD Design Challenges [J] . H. G. FENG, R. Y. ZHAN, G. CHEN, Analog Integrated Circuits and Signal Processing . 2004,第1期

机译：射频集成电路的静电放电保护：新的ESD设计挑战
4. Unified circuit modeling technique for the simulation of electrostatic discharge (ESD) injected by an ESD generator [C] . Sekine Tadatoshi, Asai Hideki, Lee John S. 2012 IEEE International Symposium on Electromagnetic Compatibility. . 2012

机译：用于模拟由ESD发生器注入的静电放电（ESD）的统一电路建模技术
5. On the investigation of materials, technology, and testing of electrostatic discharge (ESD) protection for integrated circuits. [D] . Chu, Charles Y. 2000

机译：研究材料，技术以及集成电路的静电放电（ESD）保护测试。
6. Early supported discharge after stroke in Bergen (ESD Stroke Bergen): three and six months results of a randomised controlled trial comparing two early supported discharge schemes with treatment as usual [O] . Håkon Hofstad, Bente Elisabeth Bassøe Gjelsvik, Halvor Næss, 2014

机译：卑尔根中风后早期支持性出院（ESD Stroke Bergen）：一项随机对照试验的结果分别比较了两个早期支持性出院方案和常规治疗的三个月和六个月结果
7. Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits [O] . Pengyu Lai, Xianrui Li, Hui Wang, 2019

机译：轨道基静电放电（ESD）保护电路寄生双极晶体管的研究

Electrostatic Discharge (ESD) Simulator Experiment (Testing of Some Switches/Relays for Application to an ESD Simulation Circuit)

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