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首页> 美国政府科技报告 >Use of the Reduced Precision Redundancy (RPR) Method in a Radix-4 FFT Implementation
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Use of the Reduced Precision Redundancy (RPR) Method in a Radix-4 FFT Implementation

机译：在Radix-4 FFT实现中使用精简冗余（RpR）方法

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Reduced precision redundancy (RPR), as a new method for improving fault tolerance in FPGAs, appears promising in replacing triple modular redundancy (TMR) to prevent the single event effects due to radiation in arithmetic processes. As a test of this approach, the RPR technique was used to implement a Radix-4 fast Fourier transform (FFT). This design was implemented in a Xilinx Virtex 2 FPGA in order to find the possible gain in speed and power as compared to the TMR method. This thesis deals with a 64-point Radix-4 in- place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA's modules. The point was to create a fast and small FFT module that could be altered according to specific application requirements. The implementation of the FFT was successful, managing to handle data in real time at a speed of 134MHz. Based on this FFT design, the next challenge was the implementation of TMR and RPR modules. The first attempt was the TMR structure, implemented by creating three identical replicas of the FFT and installing a voter per FFT stage. This implementation was unsuccessful due to space limitations. The next step was the alteration of the existing FFT and the creation of a smaller 8 x 8 bit butterfly module for the RPR structure. After the successful completion of this step, implementation of a RPR module with an 8/32 degree was commenced. Ambiguities and inefficient radiation protection were identified in this implementation. Finally, adopting a new RPR approach and a higher degree of 14/32, a smooth and correct RPR module was created that could work in real time, and handle data at a speed of 163MHz. Both TMR and RPR with a degree of 14/32 methods were compared, confirming the RPR's advantage in power consumption and in occupied FPGA's resources.

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