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首页> 美国政府科技报告 >Efficient Bit-Level, Word-Level, and Block-Level Systolic Arrays for Matrix-Matrix Multiplication
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Efficient Bit-Level, Word-Level, and Block-Level Systolic Arrays for Matrix-Matrix Multiplication

机译：用于矩阵乘法的高效位级，字级和块级收缩阵列

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This paper investigates the mapping of matrix-matrix multiplication onto bit level, word level and block level systolic arrays. Highly efficient and regular bit level, word level and block level systolic arrays are described. Efficiencies of many block level and word level systolic arrays reported in this paper approach 100/percent/, three times the efficiencies of systolic arrays reported previously. Bit level systolic arrays reported in this paper require less computation time than do bit level systolic arrays reported previously and, for special matrices, require less cells. Execution times of block level systolic algorithms on sixty-four-element multiprocessor agree with theory. (ERA citation 13:035538)

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