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S-1 Uniprocessor Architecture (S-1 MARK IIA).

机译：s-1单处理器架构（s-1 maRK IIa）。

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The S-1 Mark IIA uniprocessor is the second generation of a pipelined vector and scalar processing computer with a virtual address space of 2 exp 29 thirty-six bit words, addressable in quarterwords, and a physical address space of 2 exp 32 singlewords. This manual describes its native mode instruction set and an assembler for that instruction set. While a Mark IIA uniprocessor can operate alone or as part of a mulitple-instruction-stream multiple-data-stream (MIMD) multiprocessor, this manual deals only with single processor operation. It also avoids implementation-dependent details like instruction timing and numerical values corresponding to opcode mnemonics. Section 1 presents an overview of the architecture. Section 2, which assumes knowledge of the material in Section 1, divides the native mode instructions into groups, preceding each group with architectural details pertaining to that group. Section 3 describes the FASM assembler, but one can understand the assembly language examples in the previous sections without having read this description. (ERA citation 08:038320)

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