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Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect.

机译：具有两级金属互连的4H-siC JFET集成电路的处理和延长500 C测试。

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Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

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作者
Spry, D. J.; Neudeck, P. G.; Chen, L.; Lukco, D.; Chang, C. W.; Beheim, G. M.; Krasowski, M. J.; Prokop, N. F.;
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年度 2015
页码 1-4
总页数 4
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
Integrated circuits; Random access memory; Memory (computers); Chips; Silicon carbides; Jfet; Microelectronics; Decoders; Oscillators; Circuits;

机译：集成电路;随机存取存储器;存储器（计算机）;芯片;碳化硅; Jfet;微电子学;解码器;振荡器;电路;

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专利

1. Processing and Prolonged 500 ℃ Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect [J] . David J. Spry, Philip G. Neudeck, Liangyu Chen, Materials science forum . 2016,第期

机译：两层金属互连的4H-SiC JFET集成电路的加工和500℃延长测试
2. Year-long 500℃ Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits [J] . Philip G. Neudeck, David J. Spry, Michael J. Krasowski, International Journal of Microcircuits & Electronic Packaging . 2018,第4期

机译：大型4H-SiC JFET集成电路的为期一年的500℃操作演示
3. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect [J] . David J. Spry, Philip G. Neudeck, Liangyu Chen, Materials science forum . 2016,第期

机译：具有两层金属互连的4H-SiC集成电路中处理非理想性的证据
4. Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits [C] . David J. Spry, Philip G. Neudeck, Liang-Yu Chen, International Conference and Exhibition on High Temperature Electronics . 2016

机译：千小时500°C耐用的4H-SIC JFET集成电路的加工和表征
5. Electron beam testing of multilevel metal integrated circuits and electronic devices. [D] . Vitarelli, James Paul. 1997

机译：多层金属集成电路和电子设备的电子束测试。
6. Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects [O] . Hocheon Yoo, Hongkeun Park, Seunghyun Yoo, -1

机译：具有无通孔多层金属互连的高度堆叠3D有机集成电路
7. Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from-150 °C to +500 °C [O] . Philip G. Neudeck, Michael J. Krasowski, Liang-yu Chen, 2016

机译：在-150°C至+ 500°C的宽温度范围内表征6H-siC JFET集成电路

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect.

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