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Compact: Compaction of Hierarchial Chip Layouts Based on a Constraint Graph Method with Double-Sided Constraints

机译：紧凑：基于双边约束约束图法的层次芯片布局压缩

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The compaction program COMPACT used in interactive computer aided design of integrated circuit layouts is described. The compaction method is based on a constraint graph. Compaction is achieved in one or more subsequent steps by grouping the layout elements into features and then shifting these features together in horizontal or vertical direction. The nodes and edges of the graph represent the features and the constraints between the features. The compaction algorithm can handle one-sided and two-sided constraints. The two-sided constraints are resolved by backtracking. Constraints on the shift of layout elements which overlap each other are determined with a linear method. For determination of constraints of nonoverlapping elements, windowing and shadowing techniques are used to reduce computation time.

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作者
Timmermans, X. I. M.;
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年度 1983
页码 p.1-45
总页数 45
原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
Compacting; Computer aided design; Computer systems programs; Integrated circuits; Layouts; Chips; Circuit diagrams; Computer graphics;

机译：压缩;计算机辅助设计;计算机系统程序;集成电路;布局;芯片;电路图;计算机图形;

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5. A METHODOLOGY FOR VLSI DESIGN AND A CONSTRAINT-BASED LAYOUT LANGUAGE (HIERARCHICAL DESIGN) [D] . MATA, JOSE MONTEIRO DA. 1984

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6. Iterative Reconstruction of High-Dimensional Gaussian Graphical Models Based on a New Method to Estimate Partial Correlations under Constraints [O] . Vincent Guillemot, Andreas Bender, Anne-Laure Boulesteix -1

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8. Large constraint length high speed viterbi decoder based on a modular hierarchial decomposition of the deBruijn graph [R] . 1991

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Compact: Compaction of Hierarchial Chip Layouts Based on a Constraint Graph Method with Double-Sided Constraints

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