• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文OA文献 >Energy-Efficient STDP-Based Learning Circuits with Memristor Synapses
【2h】

Energy-Efficient STDP-Based Learning Circuits with Memristor Synapses

机译：具有忆阻器突触的节能型基于STDP的学习电路

代理获取
本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization.
机译：现在已被接受，具有处理器和内存分离功能的传统冯·诺依曼体系结构不适用于处理哺乳动物大脑可以有效处理的并行数据流。此外，研究人员现在设想了一种计算架构，该架构可通过实时识别时空关系并解决复杂的模式识别问题来实现对大量数据的认知处理。忆阻器交叉点阵列与标准CMOS技术集成在一起，有望产生大规模的并行和低功耗Neuromorphic计算架构。最近，在刺突神经网络（SNN）方面取得了重大进展，该过程模仿了皮质大脑中的数据处理。这些结构包括密集的神经元网络和轴突和树突之间形成的突触。此外，正在研究无监督或有监督的竞争性学习计划，以进行网络的全球培训。与软件实现相反，这些网络的硬件实现需要大量的电路开销来寻址和单独更新网络权重。取而代之的是，我们采用了受生物启发的学习规则，例如依赖于尖峰时序的可塑性（STDP），以在本地有效地更新网络权重。为了在芯片上实现SNN，我们建议在CMOS芯片的后端（BEOL）中使用密集集成的混合信号集成和发射神经元（IFN）和忆阻器的交叉点阵列。新型IFN电路已被设计为即使在峰值速率大于10 MHz的情况下，也能并行驱动忆阻突触，同时保持整体功率效率（/尖峰/突触）。我们介绍了具有忆阻器突触的IFN的电路设计细节和仿真结果，其对传入的尖峰序列的响应和STDP学习特征。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
代理获取

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号