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MULTIFERROIC NANOMAGNETIC LOGIC: HYBRID SPINTRONICS-STRAINTRONIC PARADIGM FOR ULTRA-LOW ENERGY COMPUTING

机译:多铁纳米磁性逻辑:用于超低能计算的混合自旋-铁磁范式

摘要

Excessive energy dissipation in CMOS devices during switching is the primary threat to continued downscaling of computing devices in accordance with Moore’s law. In the quest for alternatives to traditional transistor based electronics, nanomagnet-based computing [1, 2] is emerging as an attractive alternative since: (i) nanomagnets are intrinsically more energy-efficient than transistors due to the correlated switching of spins [3], and (ii) unlike transistors, magnets have no leakage and hence have no standby power dissipation. However, large energy dissipation in the clocking circuit appears to be a barrier to the realization of ultra low power logic devices with such nanomagnets. To alleviate this issue, we propose the use of a hybrid spintronics-straintronics or straintronic nanomagnetic logic (SML) paradigm. This uses a piezoelectric layer elastically coupled to an elliptically shaped magnetostrictive nanomagnetic layer for both logic [4-6] and memory [7-8] and other information processing [9-10] applications that could potentially be 2-3 orders of magnitude more energy efficient than current CMOS based devices. This dissertation focuses on studying the feasibility, performance and reliability of such nanomagnetic logic circuits by simulating the nanoscale magnetization dynamics of dipole coupled nanomagnets clocked by stress. Specifically, the topics addressed are: 1. Theoretical study of multiferroic nanomagnetic arrays laid out in specific geometric patterns to implement a “logic wire” for unidirectional information propagation and a universal logic gate [4-6]. 2. Monte Carlo simulations of the magnetization trajectories in a simple system of dipole coupled nanomagnets and NAND gate described by the Landau-Lifshitz-Gilbert (LLG) equations simulated in the presence of random thermal noise to understand the dynamics switching error [11, 12] in such devices. 3. Arriving at a lower bound for energy dissipation as a function of switching error [13] for a practical nanomagnetic logic scheme. 4. Clocking of nanomagnetic logic with surface acoustic waves (SAW) to drastically decrease the lithographic burden needed to contact each multiferroic nanomagnet while maintaining pipelined information processing. 5. Nanomagnets with four (or higher states) implemented with shape engineering. Two types of magnet that encode four states: (i) diamond, and (ii) concave nanomagnets are studied for coherence of the switching process.
机译:根据摩尔定律,切换期间CMOS设备中过多的能量消耗是继续缩小计算设备尺寸的主要威胁。在寻求基于传统晶体管的电子产品的替代方案时,基于纳米磁体的计算[1、2]成为一种有吸引力的替代方案,因为:(i)由于自旋的相关切换,纳米磁体本质上比晶体管具有更高的能源效率[3]。 (ii)与晶体管不同,磁体没有泄漏,因此没有待机功耗。然而,时钟电路中的大量能量消耗似乎是实现具有这种纳米磁体的超低功耗逻辑器件的障碍。为了缓解此问题,我们建议使用混合自旋电子学—应变电子学或应变电子纳米磁逻辑(SML)范例。对于逻辑[4-6]和存储器[7-8]以及其他信息处理[9-10]应用,它使用弹性耦合到椭圆形磁致伸缩纳米磁性层的压电层,其潜在数量可能会增加2-3个数量级与当前基于CMOS的设备相比具有更高的能源效率。本文通过模拟应力作用下偶极耦合纳米磁体的纳米级磁化动力学,研究了这种纳米磁逻辑电路的可行性,性能和可靠性。具体而言,要解决的主题是:1.对以特定几何图案布置的多铁纳米磁阵列的理论研究,以实现用于单向信息传播的“逻辑线”和通用逻辑门[4-6]。 2.在偶极耦合纳米磁铁和NAND门的简单系统中,由Landau-Lifshitz-Gilbert(LLG)方程描述的简单系统中磁化轨迹的蒙特卡罗模拟,在存在随机热噪声的情况下进行了模拟,以了解动态切换误差[11,12 ]在此类设备中。 3.对于实际的纳米磁逻辑方案,根据开关误差到达能量耗散的下限[13]。 4.利用表面声波(SAW)对纳米磁逻辑进行计时,以在保持流水线信息处理的同时,大大降低与每个多铁纳米磁体接触所需的光刻负担。 5.通过形状工程实现具有四个(或更高状态)的纳米磁体。研究了两种编码四种状态的磁体:(i)金刚石和(ii)凹形纳米磁体,以了解开关过程的相干性。

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    Fashami Mohammad Salehi;

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  • 年度 2014
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