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Challenges and Solutions for High Performance Analog Circuits with Robust Operation in Low Power Digital CMOS

机译：在低功耗数字CMOS中稳健运行的高性能模拟电路面临的挑战和解决方案

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摘要

In modern System-on-Chip products, analog circuits need to co-exist with digital circuits integrated on the same chip. This brings on a lot of challenges since analog circuits need to maintain their performance while being subjected to disturbances from the digital circuits. Device size scaling is driven by digital applications to reduce size and improve performance but also results in the need to reduce the supply voltage. Moreover, in some applications, digital circuits require a changing supply voltage to adapt performance to workloads. So it is further desirable to develop design solutions for analog circuits that can operate with a flexible supply voltage, which can be reduced well below 1V. In this thesis challenges and solutions for key high performance analog circuit functions are explored and demonstrated that operate robustly in a digital environment, function with flexible supply voltages or have a digital-like operation. A combined phase detector consisting of a phase-frequency detector and sub-sampling phase detector is proposed for phase-locked loops (PLLs). The phase-frequency function offers robust operation and the sub-sampling detector leads to low in-band phase noise. A 2.2GHz PLL with a combined phase detector was prototyped in a 65nm CMOS process, with an on-chip loop filter area of only 0.04mm^2. The experimental results show that the PLL with the combined phase detector is more robust to disturbances than a sub-sampling PLL, while still achieving a measured in-band phase noise of -122dBc/Hz which is comparable to the excellent noise performance of a sub-sampling PLL. A pulse-controlled common-mode feedback (CMFB) circuit is proposed for a 0.6V-1.2V supply-scalable fully-differential amplifier that was implemented in a low power/leakage 65nm CMOS technology. An integrator built with the amplifier occupies an active area of 0.01mm^2. When the supply is changed from 0.6V to 1.2V, the measured frequency response changes are small, demonstrating the flexible supply operation of the differential amplifier with the pulse-controlled CMFB. Next, models are developed to study the performance scaling of a continuous-time sigma-delta modulator (SDM) with a varying supply voltage. It is demonstrated that the loop filter and the quantizer exhibit different supply dependence. The loop noise performance becomes better at a higher supply thanks to larger signal swings and better signal-to-noise ratio, while the figure of merit determined by the quantization noise gets better at a lower supply voltage, thanks to the quantizer power dissipation reduction. The theoretical models were verified with simulations of a 0.6V-1.2V 2MHz continuous-time SDM design in a 65nm CMOS low power/leakage process. Finally, two design techniques are introduced that leverage the continued improvement of digital circuit blocks for the realization of analog functions. A voltage-controlled-ring-oscillator-based amplifier with zero compensation is proposed that internally uses a phase-domain representation of the analog signal. This provides a huge DC gain without significant penalties on the unity-gain bandwidth or area. With this amplifier a 4th-order 40-MHz active-UGB-RC filter was implemented that offers a wide bandwidth, superior linearity and small area. The filter prototype in a 55nm CMOS process has an active area of 0.07mm^2 and a power consumption of 7.8mW at 1.2V. The in-band IIP3 and out-of-band IIP3 are measured as 27.3dBm and 22.5dBm, respectively. A digital in-situ biasing technique is proposed to overcome the design challenges of conventional analog biasing circuits in an advanced CMOS process. A digital CMFB was simulated in a 65nm CMOS technology to demonstrate the advantages of this digital biasing scheme. Using time-based successive approximation conversion, the digital CMFB provides the desired analog output with a more robust operation and a smaller area, but without needing any stability compensation schemes like in conventional analog CMFBs. In summary, analog design techniques are continuously evolving to adapt to the integration with digital circuits on the same chip and are increasingly using digital-like blocks to realize analog functions in highly-integrated SOC chips. The signal representation in analog circuits is moving from traditional electrical signals such as voltage or current, to time and phase-domain representations. These changes make analog circuits more robust to voltage disturbances and supply variations. In addition to improved robustness, analog circuits based on timing signals benefit from the faster and smaller transistors offered by the continued feature scaling in CMOS technologies.
机译：在现代片上系统产品中，模拟电路需要与集成在同一芯片上的数字电路共存。由于模拟电路需要在受到数字电路干扰的同时保持其性能，因此带来了很多挑战。器件尺寸缩放由数字应用驱动，以减小尺寸并提高性能，但同时也需要降低电源电压。此外，在某些应用中，数字电路需要变化的电源电压以使性能适应工作负载。因此，进一步希望为模拟电路开发设计解决方案，该解决方案可以在灵活的电源电压下工作，该电源电压可以降低到1V以下。在本文中，对关键的高性能模拟电路功能的挑战和解决方案进行了探讨，并证明了它们在数字环境中能可靠运行，在灵活的电源电压下运行或具有类似数字的功能。提出了一种由相位频率检测器和子采样相位检测器组成的组合式相位检测器，用于锁相环（PLL）。相频功能可提供稳定的操作，子采样检测器可降低带内相位噪声。具有65mm CMOS工艺的带有组合鉴相器的2.2GHz PLL原型，片上环路滤波器面积仅为0.04mm ^ 2。实验结果表明，带组合鉴相器的PLL相比于子采样PLL具有更强的抗干扰能力，同时仍可测得-122dBc / Hz的带内相位噪声，可与子采样的出色噪声性能相媲美。采样PLL。提出了一种针对0.6V-1.2V电源可缩放的全差分放大器的脉冲控制共模反馈（CMFB）电路，该电路采用低功耗/漏电65nm CMOS技术实现。放大器内置的积分器的有效面积为0.01mm ^ 2。当电源从0.6V更改为1.2V时，测得的频率响应变化很小，这说明了采用脉冲控制CMFB的差分放大器的灵活电源操作。接下来，开发模型以研究具有变化电源电压的连续时间sigma-delta调制器（SDM）的性能缩放。证明了环路滤波器和量化器表现出不同的供电依赖性。较高的信号摆幅和较好的信噪比，在较高的电源下，环路噪声性能变得更好，而在较低的电源电压下，由于降低了量化器功耗，由量化噪声确定的品质因数变得更好。理论模型通过在65nm CMOS低功耗/泄漏工艺中进行的0.6V-1.2V 2MHz连续时间SDM设计仿真得到了验证。最后，介绍了两种设计技术，它们利用数字电路模块的不断改进来实现模拟功能。提出了一种具有零补偿的基于压控环振荡器的放大器，该放大器在内部使用模拟信号的相域表示。这样可提供巨大的DC增益，而不会明显损害单位增益带宽或面积。利用该放大器，实现了4阶40 MHz有源UGB-RC滤波器，可提供宽带宽，出色的线性度和较小的面积。采用55nm CMOS工艺的滤波器原型具有0.07mm ^ 2的有效面积，在1.2V电压下的功耗为7.8mW。带内IIP3和带外IIP3的测量结果分别为27.3dBm和22.5dBm。提出了一种数字原位偏置技术，以克服高级CMOS工艺中传统模拟偏置电路的设计挑战。在65nm CMOS技术中对数字CMFB进行了仿真，以证明该数字偏置方案的优势。使用基于时间的逐次逼近转换，数字CMFB可提供所需的模拟输出，具有更强健的操作和更小的面积，但无需像常规模拟CMFB那样的任何稳定性补偿方案。总而言之，模拟设计技术不断发展以适应与同一芯片上数字电路的集成，并且越来越多地使用类数字模块在高度集成的SOC芯片中实现模拟功能。模拟电路中的信号表示已从传统的电信号（例如电压或电流）转变为时域和相域表示。这些变化使模拟电路对电压扰动和电源变化更加鲁棒。除了提高鲁棒性外，基于定时信号的模拟电路还受益于CMOS技术不断扩展的特性所提供的更快，更小的晶体管。

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    Hsu Chun-Wei;

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  • 年度 2015
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  • 正文语种 {"code":"en","name":"English","id":9}
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