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Hardware/software system-on-chip co-verification platform based on logic-based environment for application programming interfacing

机译：基于基于逻辑的环境的硬件/软件片上系统协同验证平台，用于应用程序编程接口

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摘要

System-on-chip (SoC) is a single-chip that integrates hardware and software components. Hardware/software co-design and co-verification are crucial steps to ensure functional correctness of SoC design. Hardware/software co-verification technique is needed to test and decide ways to partition software and hardware components for an optimized system. Recently, field-programmable gate array (FPGA) prototyping has been proposed as a method that provides a rapid prototyping platform of SoC development and verification. SoC FPGA prototyping involves multiple cross-platform asynchronous clock domains that make SoC verification process becomes more challenging. This project implements an asynchronous firstin- first-out (FIFO) based data transfer between two hardware components which are operating in different clock domains. This implementation operates in actual FPGA and makes use of Logic-based Environment for Application Programming (LEAP) infrastructure such as communication mechanism to allow communication between hardware and software models or components. A study related to execution time characterization is done to understand the effects of hardware/software tasks partitioning on hardware/software communication, hardware execution and software execution time. Resource analysis is done on asynchronous FIFO implementation and it shows a logarithmic relationship between the logic elements and FIFO entries. An approximately linear relationship between two-way average latency and data size are shown by passing data from FPGA to host and return back the data from host to FPGA. MPEG-2 Audio Layer III (MP3) decoder case study shows with an optimum hardware/software partitioning, the co-verification platform is able to achieve a communication time of approximately 30 million cycles with 99.99 percent of the time spent originated from hardware/software communication. This result clearly shows that bidirectional communication between hardware and software plays a significant role in affecting the total communication time spent for particular application which has tasks running in both hardware and software
机译：片上系统（SoC）是集成了硬件和软件组件的单芯片。硬件/软件协同设计和协同验证是确保SoC设计功能正确性的关键步骤。需要硬件/软件协同验证技术来测试和确定为优化系统划分软件和硬件组件的方式。最近，现场可编程门阵列（FPGA）原型已被提出作为一种提供SoC开发和验证的快速原型平台的方法。 SoC FPGA原型涉及多个跨平台异步时钟域，这使得SoC验证过程变得更具挑战性。该项目在两个工作在不同时钟域的硬件组件之间实现了基于异步先进先出（FIFO）的数据传输。该实现在实际的FPGA中运行，并利用基于逻辑的应用程序编程（LEAP）基础架构环境，例如通信机制，以允许硬件和软件模型或组件之间进行通信。完成了与执行时间表征相关的研究，以了解硬件/软件任务分区对硬件/软件通信，硬件执行和软件执行时间的影响。资源分析是在异步FIFO实现上完成的，它显示了逻辑元素与FIFO条目之间的对数关系。通过将数据从FPGA传递到主机，然后将数据从主机返回到FPGA，可以显示双向平均等待时间和数据大小之间的近似线性关系。 MPEG-2音频第III层（MP3）解码器案例研究表明，通过最佳的硬件/软件分区，该共同验证平台能够实现大约3000万个周期的通信时间，其中99.99％的时间花费在硬件/软件上通讯。该结果清楚地表明，硬件和软件之间的双向通信在影响任务在硬件和软件中均运行的特定应用程序中的总通信时间中起着重要作用。

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    Teo Hong Yap;

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  • 年度 2015
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