首页> 外国专利> PROCÉDÉ DE FABRICATION DE TRANCHE SEMI-CONDUCTRICE, PROCÉDÉ DE FABRICATION D'ÉLÉMENT DE DÉTECTION DE FAISCEAU D'ÉNERGIE DE SEMI-CONDUCTEUR, ET TRANCHE SEMI-CONDUCTRICE

PROCÉDÉ DE FABRICATION DE TRANCHE SEMI-CONDUCTRICE, PROCÉDÉ DE FABRICATION D'ÉLÉMENT DE DÉTECTION DE FAISCEAU D'ÉNERGIE DE SEMI-CONDUCTEUR, ET TRANCHE SEMI-CONDUCTRICE

摘要

A through-slit is provided in a semiconductor wafer. A first virtual cutting line defines a chip portion including an energy ray sensitive region as viewed from a direction perpendicular to a first main surface. The shortest distance from a second virtual cutting line to the edge of a second semiconductor region is smaller than the shortest distance from the first virtual cutting line to the edge of the second semiconductor region. The through-slit penetrates through the semiconductor wafer in the thickness direction along the second virtual cutting line. A side surface to which a first semiconductor region 3 is exposed is formed in the chip portion by providing the through-slit. A fourth semiconductor region of a first conductivity type is provided on the side surface side of the chip portion by adding impurities to the side surface to which the first semiconductor region 3 is exposed.

著录项

  • 公开/公告号EP3680940A1

    专利类型

  • 公开/公告日2020.07.15

    原文格式PDF

  • 申请/专利权人

    申请/专利号EP18854988.5

  • 发明设计人

    申请日2018.09.05

  • 分类号

  • 国家 EP

  • 入库时间 2022-08-21 10:53:09

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