首页>
外国专利>
PROCÉDÉ DE FABRICATION DE TRANCHE SEMI-CONDUCTRICE, PROCÉDÉ DE FABRICATION D'ÉLÉMENT DE DÉTECTION DE FAISCEAU D'ÉNERGIE DE SEMI-CONDUCTEUR, ET TRANCHE SEMI-CONDUCTRICE
PROCÉDÉ DE FABRICATION DE TRANCHE SEMI-CONDUCTRICE, PROCÉDÉ DE FABRICATION D'ÉLÉMENT DE DÉTECTION DE FAISCEAU D'ÉNERGIE DE SEMI-CONDUCTEUR, ET TRANCHE SEMI-CONDUCTRICE
展开▼
展开▼
页面导航
摘要
著录项
相似文献
摘要
A through-slit is provided in a semiconductor wafer. A first virtual cutting line defines a chip portion including an energy ray sensitive region as viewed from a direction perpendicular to a first main surface. The shortest distance from a second virtual cutting line to the edge of a second semiconductor region is smaller than the shortest distance from the first virtual cutting line to the edge of the second semiconductor region. The through-slit penetrates through the semiconductor wafer in the thickness direction along the second virtual cutting line. A side surface to which a first semiconductor region 3 is exposed is formed in the chip portion by providing the through-slit. A fourth semiconductor region of a first conductivity type is provided on the side surface side of the chip portion by adding impurities to the side surface to which the first semiconductor region 3 is exposed.
展开▼