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Timing pulse circuit employing cascaded gated monostables sequenced and controlled by counter
Timing pulse circuit employing cascaded gated monostables sequenced and controlled by counter
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摘要
1,043,553. Transistor pulse-circuits. HONEYWELL Inc. March 22, 1963 [March 28, 1962], No. 11507/63. Heading H3T. A cyclic electronic timer comprises a plurality of monostable stages the output of each being coupled via one or more gates to the input of the next so as to form a closed loop and a counter having inputs from the monostable circuits and outputs to selected input gates of the closed loop so as to exercise control on the cycling. Transistor monostable circuits.-Fig. 3 shows a monostable circuit suitable for use with the invention. A negative input pulse cuts off diode 84 so that the resulting fall in potential at point A is passed via a noise threshold diode 90 and a further diode 92 to turn on the driving transistor 94. The resulting positive-going pulse at point B is passed via a similar arrangement of diodes 102, 106, 109 to turn off transistor 110 so that capacitor 116 charges negatively until the voltage at point C is clamped by a Zener diode 122 and conventional diode 120 to a potential adjustable by variation of supply - V3. At the end of the pulse at point A transistor 94 is turned off and 110 turned on, discharging capacitor 116 via variable resistor 124, thus turning off transistor 118 and initiating a negative-going pulse at E the duration of which is adjustable by variation of resistor 124 or supply voltage V3. Turn-off switching delays in transistors 94, 110 are prevented by diodes 96, 112 which avoid saturation. Closed loop timing pulse generating systems.- Fig. 1 shows a system for generating timing pulses for data processing apparatus comprising three groups of monostable stages C1A . . . C1D, C2A . . . C2D, C3A . . . C3D. At least one of the monostable stages of each group is connected via gates so as to form a closed loop capable of continuous oscillation. When the starting switch 50 is closed, a pulse produced at 62, passes gate 64 and inverter 54, giving a signal on line 25. This is also fed via gate 58, inverter 56 and gate 60 to retain inverter 54 in its present state, thus maintaining the voltage on line 25. The inputs to the gates associated with the monostable stages are such as to ensure that only monostable stages C1 are triggered at this instant. Pulses from the monostable stages step a counter 14, outputs A, #A, B, #B of which are fed to the gates associated with the monostable stages in such a way that the stages are triggered in succession until the stop switch 52 is closed when a pulse from 66 resets the bistable circuit comprising inverters 54, 56, cancelling the signal on line 25 which inhibits cycling of the closed loop and resets the counter 14. The outputs from counter 14, in the reset condition, ensure that the next cycle will start at the monostable stages C1. The output from monostable stage C2D is fed to an AND gate 38 together with the inverted output from stage C2C. The duration of output pulse from 38 is thus equal to the difference in duration of pulses from C2C, C2D and is hence adjustable by variation of supply voltage 36. Single cycle or subcycle operation.-When the one-third cycle switch 70 is closed, operation of the starting switch 50 results in a pulse from 62 being fed via gates 64 and 72 to both inverters 54, 56 which in turn feed a pulse on line 25 to trigger monostable stages C1. The duration of the pulse from 62 is sufficiently short to prevent subsequent triggering of stages C2, C3 and the use of a pulse on both sides of the bi-stable circuit comprising inverters 54, 56 prevents bi-stable switching of this circuit. When the 1 cycle switch 74 is closed, operation of the starting switch 50 changes the state of the bi-stable stage 54, 56 so that a signal on line 25 sequentially triggers the three groups of monostable stages C1, C2, C3. The bi-stable stage 54, 56 is reset after one complete cycle by signals #A, #B from the counter 14 fed to gate 76.
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