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TECHNIQUES PERMETTANT DE GÉRER L'ACCÈS À UNE MÉMOIRE D'ACCÉLÉRATEUR MATÉRIEL
TECHNIQUES PERMETTANT DE GÉRER L'ACCÈS À UNE MÉMOIRE D'ACCÉLÉRATEUR MATÉRIEL
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摘要
Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.
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