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Approach for an area-efficient and scalable CMOS performance based on advanced silicon-on-insulator (SOI), silicon-on-sapphire (SOS) and silicon-on-nothing (SON) technologies
Approach for an area-efficient and scalable CMOS performance based on advanced silicon-on-insulator (SOI), silicon-on-sapphire (SOS) and silicon-on-nothing (SON) technologies
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摘要
Device architectures for a Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor (SOI-MOSFET) were defined. They incorporated configurations of Body-Tied-Source that drastically increased the conductance that an Impact-Ionizations current sees from the body of an SOI-MOSFET. This consequently permitted the SOI-MOSFET to effectively operate at far higher operating biases.
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