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-/ MEMORY WITH LOCAL-/GLOBAL BIT LINE ARCHITECTURE AND ADDITIONAL CAPACITANCE FOR GLOBAL BIT LINE DISCHARGE IN READING
-/ MEMORY WITH LOCAL-/GLOBAL BIT LINE ARCHITECTURE AND ADDITIONAL CAPACITANCE FOR GLOBAL BIT LINE DISCHARGE IN READING
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机译：-/具有本地/全局位线结构的存储器以及用于读取中的全局位线放电的附加电容
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摘要
A memory unit including at least one global bit line connected to the sense amplifier and a plurality of memory cells grouped into a plurality of memory cell groups is provided, each of which is connected to operate on each of the memory cells in the memory cell group. Has one or more local bit lines. Each memory cell group is configured such that when the memory cells of the memory cell group are being read, one or more local bit lines of the memory cell group are provided as inputs to the logic circuit and not connected to the global bit line, and the logic circuit is The capacitance element is configured to be connected to one of the one or more global bit lines depending on the state of the one or more local bit lines of the group of memory cells.
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