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NON-VOLATILE STATIC RANDOM ACCESS MEMORY ARCHITECTURE HAVING SINGLE NON-VOLATILE BIT PER VOLATILE MEMORY BIT
NON-VOLATILE STATIC RANDOM ACCESS MEMORY ARCHITECTURE HAVING SINGLE NON-VOLATILE BIT PER VOLATILE MEMORY BIT
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机译：非易失性静态随机访问存储器体系结构每个非易失性位具有单个非易失性位
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摘要
Disclosed herein is a method of operating a non-volatile static random access NVSRAM memory formed from words. Each word includes NVSRAM cells, each of those NVSRAM cells having an SRAM cell and an electronically erasable programmable read only memory EEPROM cell. If the SRAM cells of a word have been accessed since powerup, data is read from the NVSRAM cells of that word through the SRAM cells. However, if the SRAM cells of that word have not been written since powerup, data is read from the NVSRAM cells of that word through the EEPROM cells.
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