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HYBRID OUT OF CONTEXT HIERARCHICAL DESIGN FLOW FOR HIERARCHICAL TIMING CONVERGENCE OF INTEGRATED CIRCUITS FOR OUT OF CONTEXT SIGNOFF ANALYSIS
HYBRID OUT OF CONTEXT HIERARCHICAL DESIGN FLOW FOR HIERARCHICAL TIMING CONVERGENCE OF INTEGRATED CIRCUITS FOR OUT OF CONTEXT SIGNOFF ANALYSIS
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机译：混合出上下文分层设计流，用于出于上下文签出分析而对集成电路进行分层定时收敛
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摘要
A computer-implemented method for a hierarchical design flow for deterministic or statistical timing convergence of VLSI circuits enabling design reuse, concurrency and out of context signoff analysis includes: defining, by a computing device, component clock definitions; performing static timing analysis on a lower level component of a circuit design; performing a timing closure for the lower level component based on performing the static timing analysis; generating a timing abstract associated with the lower level component; performing static timing analysis on a higher level component of the circuit design using the timing abstract and the results of the out-of-context timing analysis of the lower level component; generating smart guidance assertions based on performing the static timing analysis on the higher level component; and storing the smart guidance assertions for performing a subsequent timing analysis on the lower level component.
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