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Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
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机译：时钟偏移策略可降低动态功耗并消除同步数字VLSI设计中的保持时间违规
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摘要
This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.
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