首页> 外国专利> LOW JITTER DIGITAL PHASE LOCK LOOP WITH A NUMERICALLY-CONTROLLED BULK ACOUSTIC WAVE OSCILLATOR

LOW JITTER DIGITAL PHASE LOCK LOOP WITH A NUMERICALLY-CONTROLLED BULK ACOUSTIC WAVE OSCILLATOR

机译:具有数字控制的体声波振荡器的低抖动数字相位锁相环

摘要

A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) having a first clock input, a second clock input, and a TDC output. The DPLL includes a digital loop filter (DLF). The DLF output controls a numerically-controlled bulk acoustic wave oscillator (NCBO). The NCBO output is divided down a fractional-N divider and is fed back to the TDC. The NCBO includes a reference oscillator, a phase and/or frequency detector, a charge pump, a loop filter, a voltage-controlled bulk acoustic wave oscillator (VCBO) and a feedback fractional-N divider that has a numerical control input, which is controlled by DLF output of DPLL. The NCBO forms a stable feedback loop and have a loop bandwidth much wider than DPLL loop bandwidth. In steady state, the NCBO output frequency can be linearly numerically adjusted. An auxiliary PLL or a fractional output divider can be used to generate additional needed frequencies.
机译:数字锁相环(DPLL)包括具有第一时钟输入,第二时钟输入和TDC输出的时间数字转换器(TDC)。 DPLL包括一个数字环路滤波器(DLF)。 DLF输出控制数控体声波振荡器(NCBO)。 NCBO输出经小数N分频器分频后反馈到TDC。 NCBO包括参考振荡器,相位和/或频率检测器,电荷泵,环路滤波器,压控体声波振荡器(VCBO)和具有数字控制输入的反馈小数N分频器,该分频器为由DPLL的DLF输出控制。 NCBO形成稳定的反馈环路,并且环路带宽比DPLL环路带宽宽得多。在稳定状态下,NCBO输出频率可以线性数字调整。辅助PLL或分数输出分频器可用于生成所需的其他频率。

著录项

  • 公开/公告号US2020195259A1

    专利类型

  • 公开/公告日2020-06-18

    原文格式PDF

  • 申请/专利权人 TEXAS INSTRUMENTS INCORPORATED;

    申请/专利号US201916511107

  • 发明设计人 BEN-YONG ZHANG;

    申请日2019-07-15

  • 分类号H03L7/099;H03L7/093;H03L7/197;H03B5/32;H03B1/04;

  • 国家 US

  • 入库时间 2022-08-21 11:25:12

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