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Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation
Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation
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机译：低功耗VLSI设计使用顺序单元中的电路故障作为低电压检查以限制操作
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摘要
Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the adding a plurality of bits for sequential elements in the design including sets of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single bit error and a double bit error in the sequential elements, starting at a voltage of operation at a nominal value and gradually lowering voltage setting till a first error is detected in the sequential elements, increasing the voltage of operation by predetermined step above a voltage of first fail to achieve an optimal voltage setting of a correct operation of the design, storing this optimal voltage setting in anon-volatile memory for a subsequent use.
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