Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop

• 1. 时间到数字转换器、数字锁相环、用于操作时间到数字转换器的方法和用于数字锁相环的方法 [P] . 中国专利： CN110383185A . 2019-10-25
• 2. 全数字锁相环、时间数字转换器模块、错误防止方法及校准方法 [P] . 中国专利： CN101414821A . 2009-04-22
• 3. TIME-TO-DIGITAL CONVERTER, DIGITAL PHASE-LOCKED LOOP, METHOD FOR OPERATING A TIME-TO-DIGITAL CONVERTER, AND METHOD FOR A DIGITAL PHASE-LOCKED LOOP [P] . 世界知识产权组织专利： WO2018158614A1 . 2018-09-07

  机译： 时间数字转换器，数字锁相环，操作时间数字转换器的方法以及数字锁相环的方法

• 4. TIME-TO-DIGITAL CONVERTER, DIGITAL PHASE-LOCKED LOOP, METH-OD FOR OPERATING A TIME-TO-DIGITAL CONVERTER, AND METHOD FOR A DIGITAL PHASE-LOCKED LOOP [P] . 美国专利： US2019384230A1 . 2019-12-19

  机译： 时间数字转换器，数字锁相环，用于操作时间数字转换器的方法和用于数字锁相环的方法

• 5. - - All-Digital Phase-Locked Loop with Fine Multi-Sampling Time-to-Digital Converter and Method for Operating thereof [P] . 韩国专利： KR101617088B1 . 2016-05-02

  机译： --具有精细多采样时间数字转换器的全数字锁相环及其操作方法

• 1. PULSE SHRINKING TIME-TO-DIGITAL CONVERTER FOR UWB APPLICATION [J] . Chen Chao, Meng Shengwei, Xia Zhenghuan, 电子科学学刊（英文版） . 2014,第003期
• 2. A 2.4-GHz all-digital phase-locked loop with a pipeline-???￡ time-to-digital converter [J] . Zixuan Wang, Shanwen Hu, Zhikuang Cai, IEICE Electronics Express . 2017,第6期
• 3. Low-power, wide-range time-to-digital converter for all digital phase-locked loops [J] . Jeong C.-H., Kwon C.-K., Kim H., Electronics Letters . 2013,第2期
• 4. A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop [J] . Wu Jin, Wang Chao, Shi Shu-fang, IETE Journal of Research . 2017,第3期
• 5. A novel Time-to-Digital Converter for All Digital Phase-Locked Loop [C] . GAI Lin-chong, CHEN Lan, WANG Hai-yong IEEE International Conference on Solid-State and Integrated Circuit Technology . 2018
• 6. A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution. [D] . Lee, Min Jae. 2008
• 7. An Accurate Timing Alignment Method with Time-to-Digital Converter Linearity Calibration for High-Resolution TOF PET [O] . Hongdi Li, Chao Wang, Shaohui An, -1
• 8. A Delay Locked Loop for Time-to-Digital Converters with Quick Recovery and Low Hysteresis [O] . Bjorn Van Bockel, Jeffrey Prinzie, Ying Coa, 2019

• 1. A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP [J] . Yu Guangming Wang Yu Yang Huazhong . 电子科学学刊：英文版 . 2011,第3期
• 2. A high-precision and 10 bit two-step Time-to-Digital Converter for TOF application [J] . YE Xuefeng ,TANG Lizhen ,WANG Yang . 太赫兹科学与电子信息学报 . 2021,第003期
• 3. A high-precision and 10 bit two-step Time-to-Digital Converter for TOF application [J] . YE Xuefeng ,TANG Lizhen ,WANG Yang . 太赫兹科学与电子信息学报 . 2021,第003期
• 4. Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution [J] . Chin-Hsin Lin ,Marek Syrzycki . 电路与系统（英文） . 2011,第4期
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• 6. 应用于全数字锁相环的时间数字转换器研究与设计 [A] . 庄庆科 . 2017