首页> 外国专利> Low voltage (power) junction FET with all-around junction gate

Low voltage (power) junction FET with all-around junction gate

机译：低压（功率）结型FET，具有全面的结型栅极

页面导航

摘要
著录项
相似文献

摘要

A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

机译：一种用于制造半导体器件的方法，包括：在半导体衬底上形成底部源极/漏极区;形成从底部源极/漏极区垂直延伸的沟道区;从沟道区的上部生长顶部源极/漏极区;从栅极区域的下部在其下方生长栅极区域，其中栅极区域在沟道区域的多于一侧。

著录项

公开/公告号US10573648B2

专利类型
公开/公告日2020-02-25

原文格式PDF
申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;
展开▼

申请/专利号US201815992507
发明设计人 KARTHIK BALAKRISHNAN;BAHMAN HEKMATSHOARTABARI;ALEXANDER REZNICEK;JENG-BANG YAU;
展开▼

申请日2018-05-30
分类号H01L29/808;H01L27/092;H01L27/112;H01L27/06;H01L27/098;H01L29/08;H01L29/06;H01L29/66;H01L29/786;H01L29/423;H01L29/10;H01L27/085;H01L29/04;
国家 US
入库时间 2022-08-21 11:28:14

相似文献

专利
外文文献
中文文献