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Exactly-once transaction semantics for fault tolerant FPGA based transaction systems

机译:基于容错FPGA的事务系统的一次精确事务语义

摘要

#$%^&*AU2019201592A120191010.pdf#####1002480106 ABSTRACT EXACTLY-ONCE TRANSACTION SEMANTICS FOR FAULT TOLERANT FPGA BASED TRANSACTION SYSTEMS 5 This disclosure relates generally to methods and systems for providing exactlyonce transaction semantics for fault tolerant FPGA based transaction systems. The systems comprise middleware components in a server as well as client end. The server comprises Hosts and FPGAs. The FPGAs control transaction execution 10 (the application processing logic also resides in the FPGA) and provide fault tolerance with high performance by means of a modified TCP implementation. The Hosts buffer and persist transaction records for failure recovery and achieving exactly-once transaction semantics. The monitoring and fault detecting components are distributed across the FPGA's and Hosts. Exactly-once 15 transaction semantics is implemented without sacrificing performance by switching between a high performance mode and a conservative mode depending on component failures. PCIE switches for connectivity between FPGAs and Hosts ensure FPGAs are available even if Hosts fail. When FPGA's provide higher processing elements and memory, the Hosts may be eliminated. 20 To be published with FIG.2A1/24 Client/ Client/ Server /System Client Application Client/ Client Appli::ation Client Application _ EQUEST (CLID, RN) RESPONSE (CLID, RN)' NOTIFICATION (CLID, RN, N) NOTIFICATION (CLID, RN, N+1) NOTIFICATION (CLID, RN, N+2) ACKNOWLEDGE RESPONSE (CLID,RN,RN) ACKNOWLEDGE NOTIFICATION (CLID,RNN ,__-----ACKNOWLEDGE NOTIFICATION (CLID,RNN+l) ACKNOWLEDGENOTIFICATION(CLID,RN,N+2) FIG.1 (PRIOR ART)
机译:#$%^&* AU2019201592A120191010.pdf #####1002480106抽象容错的完全一次交易语义基于FPGA的交易系统5本公开总体上涉及用于精确地提供信息的方法和系统。基于容错FPGA的事务系统的一次事务语义。的系统包括服务器以及客户端中的中间件组件。的服务器包括主机和FPGA。 FPGA控制事务执行10(应用程序处理逻辑也驻留在FPGA中)并提供故障通过修改的TCP实现实现高性能的高容错性。主机缓冲并保留事务记录,以进行故障恢复和实现一次交易语义。监控与故障检测组件分布在FPGA和主机之间。一次在不牺牲性能的情况下实现了15种事务语义在高性能模式和保守模式之间切换,具体取决于关于组件故障。 PCIE交换机可实现FPGA与主机之间的连接即使主机发生故障,也要确保FPGA可用。当FPGA提供更高的处理单元和内存,可以省去主机。20与图2A一起发布1/24客户/客户/服务器/系统客户端应用程序客户端/客户应用程序:: ation客户应用程序>许可证_ EQUEST(CLID,RN)响应(CLID,RN)'通知(CLID,RN,N)通知(CLID,RN,N + 1)通知(CLID,RN,N + 2)应答响应(CLID,RN,RN)确认通知(CLID,RNN,__-----确认通知(CLID,RNN + 1)确认遗传化(CLID,RN,N + 2)图1(现有技术)

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