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Layout of domain effect transistor, method of making and using layout of domain effect transistor and related software
Layout of domain effect transistor, method of making and using layout of domain effect transistor and related software
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机译：区域效应晶体管的布局，制造和使用区域效应晶体管的布局的方法及相关软件
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摘要
An apparatus comprising an array of field-effect transistors, each field-effect transistor comprising a channel, source and drain electrodes configured to enable a flow of electrical current through the channel, and a gate electrode configured to enable the flow of electrical current to be varied, the gate electrode separated from the channel by a dielectric material configured to inhibit a flow of electrical current between the channel and gate electrode, wherein the gate electrode of each field-effect transistor is connected in parallel to the gate electrodes of the other field-effect transistors in the array, and wherein a respective two-terminal current-limiting component is coupled to each gate electrode such that, in the event that a defect in the dielectric material of a particular field-effect transistor allows a leakage current to flow between the channel and gate electrode of that field-effect transistor, the respective two-terminal current-limiting component limits the magnitude of the leakage current so that the other field-effect transistors in the array are substantially unaffected by the leakage current.
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