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METHOD FOR STRUCTURE OF MIN-SUM VERIFICATION NODE FOR DECODERS LDPC PARALLELIZED WITH RECURSIVE STRUCTURE, AND DISTRIBUTED CHECK
METHOD FOR STRUCTURE OF MIN-SUM VERIFICATION NODE FOR DECODERS LDPC PARALLELIZED WITH RECURSIVE STRUCTURE, AND DISTRIBUTED CHECK
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机译：具有递归结构的解码器LDPC最小和校验节点的结构方法及分布式检查
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摘要
new method for min-sum verification node structure for low density parity-check (ldpc) decoders paralleled with recursive structure and distributed verification, which allows design of a verification node which produces the exact output for the min-sum algorithm whose size grows linearly and whose latency grows logarithmically with the number of parity bits in the code. where a distribution of the operations needed to calculate the verification node result for associative, commutative, but not invertible operations based on the computation of the min-sum verification nodes is proposed and described as a divide and conquer algorithm, which can be justified by the merge-sort algorithm, such algorithm can be implemented in hardware with area and power complexity and latency, in order to simplify the verification node in the min-sum algorithm and its variations, obtaining a parallelable structure for determining the message of the verification node.
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