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MODIFYING A MANUFACTURING PROCESS OF INTEGRATED CIRCUITS BASED ON LARGE SCALE QUALITY PERFORMANCE PREDICTION AND OPTIMIZATION
MODIFYING A MANUFACTURING PROCESS OF INTEGRATED CIRCUITS BASED ON LARGE SCALE QUALITY PERFORMANCE PREDICTION AND OPTIMIZATION
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机译：基于大规模质量性能预测和优化的集成电路制造过程的修改
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摘要
A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.
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