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Method and system for performing incremental post layout simulation with layout edits
Method and system for performing incremental post layout simulation with layout edits
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机译：通过布局编辑执行增量后期布局仿真的方法和系统
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摘要
An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.
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