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Method for organizing, controlling, and reporting on design mismatch information in IC physical design data

机译:IC物理设计数据中设计失配信息的组织,控制和报告方法

摘要

Systems and methods allow an IC design process to continue in the face of errors while those errors are being investigated and fixed in the actual design data. Potential mismatches can be categorized and a user can choose which action (if any) to take when a specific mismatch is discovered. A set of potential mismatches and their action settings can be aggregated into a higher level setting that the end user of the system can choose during different stages of a design project. A record of the mismatches that have been encountered, the design elements that are involved in each mismatch, and what action where taken to repair the mismatch is kept and maintained.
机译:系统和方法允许在面对错误的同时继续进行IC设计过程,同时对这些错误进行调查并将其固定在实际设计数据中。可以对潜在的不匹配进行分类,并且用户可以选择发现特定不匹配时采取的操作(如果有)。一组潜在的不匹配及其动作设置可以汇总到一个更高级别的设置中,系统的最终用户可以在设计项目的不同阶段中进行选择。记录并记录已遇到的不匹配项,每个不匹配项所涉及的设计元素以及采取何种措施来修复不匹配项。

著录项

  • 公开/公告号US10339259B2

    专利类型

  • 公开/公告日2019-07-02

    原文格式PDF

  • 申请/专利权人 SYNOPSYS INC.;

    申请/专利号US201514868342

  • 发明设计人 MARK WILLIAM BALES;

    申请日2015-09-28

  • 分类号G06F17/50;G06F7/50;G06F11/36;G06F11/07;G06F11;G06F7;

  • 国家 US

  • 入库时间 2022-08-21 12:14:31

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