Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit

• 1. 用于对集成电路进行统计建模的方法与系统 [P] . 中国专利： CN1770167A . 2006-05-10
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• 3. Modeling of sequential circuit devices of multi-clock domain IC design for a transient vectorless power analysis [P] . 美国专利： US10460055B1 . 2019-10-29

  机译： 多时钟域IC设计的时序电路器件建模，用于无瞬态矢量分析

• 4. Method and system for functional verification and power analysis of clock-gated integrated circuits [P] . 美国专利： US9928323B2 . 2018-03-27

  机译： 时钟门控集成电路的功能验证和功率分析的方法和系统

• 5. METHOD AND SYSTEM FOR FUNCTIONAL VERIFICATION AND POWER ANALYSIS OF CLOCK-GATED INTEGRATED CIRCUITS [P] . 美国专利： US2017344682A1 . 2017-11-30

  机译： 时钟门集成电路的功能验证和功率分析的方法和系统

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