首页> 外国专利> STATE TRANSITION COMPRESSION MECHANISM TO EFFICIENTLY COMPRESS DFA BASED REGULAR EXPRESSION SIGNATURES

STATE TRANSITION COMPRESSION MECHANISM TO EFFICIENTLY COMPRESS DFA BASED REGULAR EXPRESSION SIGNATURES

机译:基于状态转换的压缩机制,可有效压缩基于DFA的常规表达签名

摘要

A signature matching hardware accelerator system comprising one or more hardware accelerator circuits, wherein each of the hardware accelerator circuit utilizes a compressed deterministic finite automata (DFA) comprising a state table representing a database of digital signatures defined by a plurality of states and a plurality of characters, wherein the plurality of states are divided into groups, each group comprising a leader state having a plurality of leader state transitions and one or more member states, each having a plurality of member state transitions is disclosed. The hardware accelerator circuit comprises a memory circuit configured to store a single occurrence of a most repeated leader state transition within each group, the unique leader state transitions comprising the leader state transitions that are different from the most repeated leader state transition within the respective group; and leader transition bitmasks associated respectively with the leader states within each group.
机译:一种包括一个或多个硬件加速器电路的签名匹配硬件加速器系统,其中,每个硬件加速器电路利用压缩的确定性有限自动机(DFA),该状态机代表表示由多个状态和多个状态定义的数字签名的数据库的状态表。公开了一种字符,其中将多个状态划分为组,每组包括具有多个领导状态过渡和一个或多个成员状态的领导状态,每个成员状态具有多个成员状态过渡。硬件加速器电路包括存储电路,该存储电路被配置为存储每个组中最重复的领导者状态转变的一次出现,唯一的领导者状态转变包括与相应组中最重复的领导者状态转变不同的领导者状态转变。和分别与每个组中的领导者状态相关联的领导者转换位掩码。

著录项

  • 公开/公告号EP3264716B1

    专利类型

  • 公开/公告日2019-05-22

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号EP20170175598

  • 发明设计人 SUBRAMANIAN SHIVA SHANKAR;LIN PINXING;

    申请日2017-06-12

  • 分类号H04L29/06;

  • 国家 EP

  • 入库时间 2022-08-21 12:29:30

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