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TRANSISTOR BASED ON TWO-DIMENSIONAL MATERIAL AND PREPARATION METHOD THEREFOR, AND TRANSISTOR ARRAY DEVICE

机译:基于二维材料的晶体管及其制备方法和晶体管阵列装置

摘要

Provided is a transistor based on a two-dimensional material, comprising an insulating substrate (10), and a source electrode (11) and a drain electrode (12) being provided at two ends of the insulating substrate (10), wherein a channel (13) is provided between the source electrode (11) and the drain electrode (12), and the middle part of the channel (13) is provided with a first two-dimensional material layer (131); a second two-dimensional material layer (132) in a channel area provided on one side of the first two-dimensional material layer (131) and connected to the source electrode (11), and a third two-dimensional material layer (133) in a channel area provided at the other side of the first two-dimensional material layer (131) and connected to the drain electrode (12), wherein the three two-dimensional material layers are an integral film layer of the same material; and a gate dielectric layer (14) and a grid electrode (15) provided on the first two-dimensional material layer (131). The thickness of the second two-dimensional material layer (132) and the thickness of the third two-dimensional material layer (133) are both greater than the thickness of the first two-dimensional material layer (131). In the transistor structure, the second and third two-dimensional material layers in contact with the source and drain electrodes are thicker, so that the contact resistance can be reduced, whereas the first two-dimensional material layer in the middle part of the channel is thinner than the contact areas, thereby ensuring a high migration rate and the modulation of the gate on the channel at the same time. Further provided are a preparation method for a transistor based on a two-dimensional material and an application thereof.
机译:提供了一种基于二维材料的晶体管,包括绝缘基板(10),以及在绝缘基板(10)的两端设置有源电极(11)和漏电极(12),其中,沟道在源电极(11)和漏电极(12)之间设置有(13),沟道(13)的中部设置有第一二维材料层(131)。设置在第一二维材料层(131)的一侧并与源电极(11)连接的沟道区域中的第二二维材料层(132)和第三二维材料层(133)在设置在第一二维材料层(131)的另一侧并与漏电极(12)连接的沟道区域中,三个三维材料层是相同材料的整体膜层。栅极介电层(14)和栅极(15)设置在第一二维材料层(131)上。第二二维材料层(132)的厚度和第三二维材料层(133)的厚度均大于第一二维材料层(131)的厚度。在晶体管结构中,与源电极和漏电极接触的第二二维材料层和第三二维材料层较厚,从而可以减小接触电阻,而沟道中间部分的第一二维材料层为比接触区域更薄,从而确保了高迁移率并同时对沟道上的栅极进行了调制。还提供了一种基于二维材料的晶体管的制备方法及其应用。

著录项

  • 公开/公告号WO2018195761A1

    专利类型

  • 公开/公告日2018-11-01

    原文格式PDF

  • 申请/专利权人 HUAWEI TECHNOLOGIES CO. LTD.;

    申请/专利号WO2017CN81821

  • 发明设计人 ZHAO CHONG;XU HUILONG;ZHANG CHENXIONG;

    申请日2017-04-25

  • 分类号H01L27/02;H01L21/77;

  • 国家 WO

  • 入库时间 2022-08-21 12:42:09

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