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A LOW COST, ECONOMICAL, REAL TIME SELF-HEALING APPROACH FOR RAM BASED ON DYNAMIC SPARE ALLOCATION USING MICROCONTROLLER
A LOW COST, ECONOMICAL, REAL TIME SELF-HEALING APPROACH FOR RAM BASED ON DYNAMIC SPARE ALLOCATION USING MICROCONTROLLER
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机译：基于微控制器动态备用分配的低成本，经济，实时的RAM自愈方法
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摘要
In todays digital era, with the advancement & development of VLSI and fabrication technologies, the need of memories inside the system-on-chip are increasing, as a basic need. The miniaturization of the whole system, on a single chip is easier than the days when resources were limited. Therefore, this is a need of hour to embed the self-test and repair structure in the design for the efficient and correct operation i.e. the need of a low cost, economical, real time self-healing approach for RAM based on dynamic spare allocation. This structure could test, diagnose and repair the chip itself for the possible errors that makes it more effective in comparison with on- site testing or offsite testing. This method is also economically effective, as compared to external test equipment i.e. automatic test equipment. The circuit that is embedded inside the chip to test itself, is called built in self-test (BIST) circuitry and the action of its fault repairing is called built in self-repair (BISR). The action of Memory BIST (MBIST) is quite different, as compared to Logic- BIST (LBIST). With the course of time MBIST/ MBISR and supporting technologies have evolved immensely but the fact is that the basic model of testing and repair still remains user-centric. This leads to numerous inevitable issues pertaining to present fault diagnosis and repair that collaboratively seems to cease the desired growth of VLSI testing. The presented work focuses on both, MBIST and MBISR and divided into four main tasks: first, testing of memory under test, second, fault collection process, third, built in redundancy analysis (BIRA) that covers redundancy analysis for available redundant memory and forth was to verify and evaluate the performance metrics of this repairing action in terms of repair rate, total repair time and area overhead. In this work a system prototype was developed which deals with total 56 bytes-RAM of RTC-DS1307. This RAM is interfaced with PIC-18F452 microcontroller and the MMBISR module of the design can allocate the spare to faulty memory, according to their precedence marked by precedency analyzer. The implemented hardware also mapped the faulty locations with repaired one in such a way that new updated locations could be used for further memory operations. The execution stage of the fault collection and repair is also dynamic so it gives the advantage over other static approaches in which fault dictionary remains static.
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