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Pipeline depth exploration in a register transfer level design description of an electronic circuit

机译:电子电路寄存器传输级设计中的管道深度探索

摘要

A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.
机译:提供了用于电路设计的输入寄存器和输出寄存器的列表。通过遍历每个输入寄存器的输出连接路径并用电线替换输出连接路径中的任何寄存器,可以修改电路设计,除非该寄存器是列出的输出寄存器。确定用于修改的电路设计的初始总循环时间值。修改后的电路设计的门级描述是通过具有初始总周期时间值的宏综合获得的。然后改变用于修改的电路设计的总循环时间值,以便确定修改的电路设计的理论极限。对于给定的总循环时间值,当修改的电路设计的宏综合中出现负松弛时,将达到理论极限。基于该理论极限,确定电路设计的最小管线深度。

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